Monday, January 28, 2008

latch fundamentals

Difference between latch & flip flop

 Latches are level sensitive i.e. the output captures the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes.
 Flip-Flops are edge sensitive i.e. flip flop will store the input only when there is a rising or falling edge of the clock.
 A positive level latch is transparent to the positive level(enable), and it latches the final input before it is changing its level(i.e. before enable goes to '0' or before the clock goes to -ve level.)
 A positive edge flop will have its output effective when the clock input changes from '0' to '1' state ('1' to '0' for negative edge flop) only.

Advantages of latch design
 Latches are faster, flip flops are slower.
 Latches take less gates (less power) to implement than flip-flops.
 Latch facilitate time borrowing or cycle stealing whereas flip flops allow
synchronous logic.

latch timings ( Recovery and Removal )
Recovery Time
 Recovery specifies the minimum time that an asynchronous control input pin must be held stable after being de-asserted and before the next clock (active-edge) transition.
 Recovery time specifies the time the inactive edge of the asynchronous signal has to arrive before the closing edge of the clock.
 Recovery time is the minimum length of time an asynchronous control signal (eg.preset) must be stable before the next active clock edge. The recovery slack time calculation is similar to the clock setup slack time calculation, but it applies asynchronous control signals.

Removal Time
 Removal specifies the minimum time that an asynchronous control input pin must be held stable before being de-asserted and after the previous clock (active-edge) transition.
 Removal time specifies the length of time the active phase of the asynchronous signal has to be held after the closing edge of clock.
 Removal time is the minimum length of time an asynchronous control signal must be stable after the active clock edge. Calculation is similar to the clock hold slack calculation, but it applies asynchronous control signals

Time borrowing in latches
Time borrowing is a concept that is used in latch based pipelines in which you typically have 2 stages of combinatorial surrounded by latches. If the first combinational piece of logic has a much longer delay than the second one, you can borrow some of the time of the second part to the first part

Example :
R2 = R0 * R1

Asume the instruction requiring two cycles to multiply and store the final result into R2. If store to R2 can be done in half cycle, then the multiplication can be allowed to extend to 1 1/2 cycles.

Hence, we can have

Pos latch - Mul combo1 - Neg Latch - Mul combo2 - Pos Latch - No logic - Neg Latch - Store combo - Pos Latch
with Mul combo1+Mul combo 2 < 1.5 clk cycles.
The multiply need be finished only before the second pos latch closes, so that the correct data passes onto the neg latch.

Instead of
Pose reg - Mul combo1&2 - Pos Reg - Store Combo - Pos Reg

However, not many people use time borrowing in multipliers, reasons evident for the following section of code, where R2 is required to be ready in 1 cycle.
R2 = R0 * R1
R4 = R2 * R3

Design and scan issue with latcehs
 Latches are not friendly with DFT tools. Minimize inferring of latches if your design has to be made testable. Since enable signal to latch is not a regular clock that is fed to the rest of the logic. To ensure testability, you need to use OR gate using "enable" and "scan_enable" signals as input and feed the output to the enable port of the latch
 Static timing analyzers typically make assumptions about latch transparency. If one assumes the latch is transparent (i.e.triggered by the active time of clock,not triggered by just clock edge), then the tool may find a false timing path through the input data pin. If one assumes the latch is not transparent, then the tool may miss a critical path.
 If target technology supports a latch cell then race condition problems are minimized. If target technology does not support a latch then synthesis tool will infer it by basic gates which is prone to race condition. Then you need to add redundant logic to overcome this problem. But while optimization redundant logic can be removed by the synthesis tool ! This will create endless problems for the design team
 Latches should not be used unless absolutely necessary. In most cases, a flip-flop will work just as well. When synthesizing designs, be especially careful to avoid accidentally inferring a latch when one is not intended. The problem with latches centers around the transparency issue. In the circuit shown in Figure, if Gate A and Gate B both go low, we might have an oscillator.


1 comment:

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#edge
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