Wednesday, January 23, 2008

VLSI Knowledge

VLSI Knowledge

Digital Basics
Latch fundamentals
Flip Flops
Different types of flip flops, RS, JK, D, T etc.
Conversion of one flip flop to other
Registers with Flip Flops (timing requirements)
setup time requirement
Hold time requirement
Negative hold time : The value on the input can change *before* the clock edge and still be carried to the output. It means that the window in which the input signal has to be held stable ends before the arrival of the clock edge. This happens if the propagation delay on the data path is guaranteed to be longer than the propagation of the clock to the same flip-flop. It is far easier to guarantee relative delays on a monolithic chip than it is to guarantee minimum delays at the board level where you have different chips. For that reason, it is desirable for the chip manufacturers to make the hold times zero or negative by careful use of delays

Counters

Clock dividers

Divide by 3.5 clock divider

Statemachines
Sequence detectors
Hazards
Adders, subtractors, multipliers, dividers

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